1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a multi-level type nonvolatile semiconductor memory device for storing data of not smaller than 2 bits (=4 values) in a memory cell.
2. Description of the Related Art
Accompanying an increase in the number of functions of various portable electronic devices and home appliances, an increasing importance has been placed on the technology for integrating a logic LSI as represented by a one-chip microcomputer with a nonvolatile semiconductor memory device which maintains the data stored even when a connection to the power supply is broken.
In general, nonvolatile semiconductor memories can be represented by an EEPROM (electrically erasable and programmable read only memory) that can electrically rewrite and erase data and a flash memory that can electrically erase data at one time. Both the EEPROM and the flash memory use basically the same MOS-type memory cell structure. That is, they have a structure in which an electrically insulated floating gate is formed on a gate-insulating film (generally, an oxide film) formed on a channel region between a pair of impurity-diffused regions (source and drain) formed in a semiconductor substrate, and a control gate (gate electrode) is provided thereon via an insulating film. In such nonvolatile memories of the MOS type, a predetermined voltage is applied to the control gate to apply an intense electric field relative to the channel region, so that the floating gate captures an electric charge so as to be electrically charged into a predetermined type of conduction thereby to store the data. When the electric charge in the floating gate is removed, the initial state is resumed and the data is erased.
A polysilicon film is typically used as a floating gate, but it has been known that the same effect can also be obtained even by using a silicon nitride film instead of the polysilicon film. That is, the device can be electrically charged into a predetermined type of conduction (in other words, data is stored) by causing the electric charge captured at the capturing center (trap) to exit in the interface between the gate oxide film and the silicon nitride film formed on the gate oxide film. A nonvolatile memory of the MNOS (metal-nitride-oxide semiconductor) type is one obtained by forming a control gate electrode on the silicon nitride film.
In the MNOS-type nonvolatile memory, however, the silicon nitride film for capturing the electric charge is in contact with the control gate electrode and causes a problem in that the electric charge accumulated in the silicon nitride film can easily leak. In order to cope with this problem, there was devised a nonvolatile memory of the MONOS (metal-oxide-nitride-oxide semiconductor) type obtained by forming an insulating film (generally, an oxide film) between the silicon nitride film and the control gate electrode.
Owing to the technology for integration, in recent years, there have been developed transistors having a gate electrode measuring not larger than 1 xcexcm. In the EEPROM, too, floating gates and control gates can be formed in fine sizes. At present, however, the technology has been accompanied by a limit of from 0.35 xcexcm to 0.5 xcexcm from the standpoint of mass production.
As another form of increasing the degree of integration, furthermore, a multi-level type nonvolatile semiconductor memory (multi-value memory) has been developed, which is so constituted that an increased amount of data is stored in a memory cell instead of finely forming the elements. In the multi-value memory, the amount of electric charge accumulated in the floating gate is adjusted in order to control the threshold value of the memory depending upon the data that are to be stored. In a heretofore known binary memory (in which each memory cell stores data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d), when, for example, an electric charge is accumulated in the floating gate, the threshold value of the memory cell becomes not smaller than 4 V, and no drain current flows when a voltage of 3 V is applied to the control gate, a voltage of 5 V is applied to the drain region and a voltage of 0 V is applied to the source region. When no electric charge is accumulated in the floating gate, however, the threshold value of the memory cell becomes not larger than 1 V and a drain current flows. In a multi-value memory, for example, in the case of a quaternary memory, the data is stored by controlling the threshold voltage of the memory cell to be 0.5 V, 1.5 V, 2.5 V and 3.5 V. The multi-value memories include those of the floating gate type, MNOS type, MONOS type and the like.
However, a limitation is imposed on increasing the values; i.e., the reliability decreases if data are stored in too large amounts in a memory cell.
To increase the values by using the above-mentioned MONOS-type nonvolatile memory, furthermore, a voltage applied to the gate electrode is suitably changed to adjust the amount of electric charge captured by the silicon nitride film to thereby realize memory states of many stages depending upon the amount of electric charge that is captured.
As the thickness of the film (silicon nitride film in this case) for capturing electric charge decreases, however, the amount of electric charge that is captured undergoes a large change, and depends upon a slight change in the voltage applied to the gate electrode, making it very difficult to adjust the amount of electric charge that is captured. Moreover, the stored data is detected through a slight difference in the amount of electric charge that is captured and, hence, even a slight leakage of charge from the trap gives rise to the occurrence of data corruption.
As prior art that has heretofore been known, furthermore, Japanese Unexamined Patent Publication (Kokai) No. 5-55596 discloses a MONOS-type nonvolatile memory equipped with many laminated films obtained by alternatingly forming silicon oxide films and silicon nitride films one upon the other to capture the electric charge. This nonvolatile memory is able to maintain reliability for extended periods of time by enhancing its performance for holding electric charge. However, the art disclosed here does not teach storing data on many levels.
As another prior art, Japanese Unexamined Patent Publication (Kokai) No. 9-74146 discloses a nonvolatile memory of the MONOS structure having a silicon nitride film sandwiched between two silicon oxide films to accumulate the electric charge between the control gate and the semiconductor substrate. In this nonvolatile memory, a voltage applied to the control gate is changed to adjust the amount of electric charge accumulated in the silicon nitride film thereby to store multi-value data depending upon the amount of electric charge that is accumulated. However, the memory cell disclosed here has only one silicon nitride film that works to accumulate the electric charge. It is therefore likely that the amount of electric charge accumulated in the silicon nitride film undergoes a change to a large extent, making it difficult to adjust the amount of electric charge that is accumulated.
As a further prior art, Japanese Unexamined Patent Publication (Kokai) No. 8-235886 discloses technology for storing data of three or more values in a memory cell having a charge-accumulating layer in a nonvolatile memory of the floating gate-type or the MNOS-type. Even in the technology disclosed here, however, there is provided only one floating gate layer or a silicon nitride film for accumulating the electric charge, from which it is considered that it will be difficult to adjust the amount of electric charge that is accumulated causing a fluctuation in the accumulated amount of electric charge as described above.
As a still further prior art, Japanese Unexamined Patent Publication (Kokai) No. 7-273227 discloses a nonvolatile memory of a structure equipped with two floating gate layers to accumulate electric charge between the control gate and the channel region. In the nonvolatile memory disclosed here, the amount of electric charge stored in the two floating gate layers is adjusted to store multi-value data, and the threshold voltage of the memory cell is so controlled as to change by a predetermined value for every increase in the value. In the nonvolatile memory of the floating gate type, a preset threshold voltage decreases due to a leakage of the accumulated electric charge giving rise to the occurrence of data corruption as in the nonvolatile memories of the MNOS type and MONOS type. When the threshold voltage is high, in particular, the amount of drop increases due to the leakage of charge causing the data to be corrupted more frequently. In the art disclosed here, the threshold voltage changes by a predetermined value every time the value increases by one. When the threshold voltage is high, in particular, it is more likely that the data will be corrupted.
As a yet further prior art, Japanese Unexamined Patent Publication (Kokai) No. 8-83855 discloses a nonvolatile memory equipped with two floating gate layers that work to accumulate the electric charge as in the above-mentioned Japanese Unexamined Patent Publication (Kokai) No. 7-273227. The art disclosed here involves the same problems as those described above.
As a further prior art, Japanese Unexamined Patent Publication (Kokai) No. 6-13628 discloses a semiconductor memory of the MNOS type or the MONOS-type. This semiconductor memory has been highly integrated in order to increase the yield of production. However, the art disclosed here does not at all teach storing the data on multi-levels. Besides, since there is provided only one silicon nitride film for accumulating the electric charge, it will be difficult to adjust the amount of electric charge causing a fluctuation in the accumulated amount of electric charge as described above.
As another prior art, Japanese Unexamined Patent Publication (Kokai) No. 7-169865 discloses a nonvolatile memory having a structure in which a floating gate is formed on the side surface of a protruded portion or a recessed portion on a semiconductor substrate to work as a layer for accumulating the electric charge, and a control gate is provided covering the floating gate as in the above-mentioned Japanese Unexamined Patent Publication (Kokai) No. 6-13628. It is, however, considered that the technology disclosed here involves the same problems as those described above.
A principal object of the present invention is to provide a nonvolatile semiconductor memory device capable of storing desired multi-value data by easily and reliably adjusting the amount of electric charge that is captured while preventing the occurrence of inconveniences such as data corruption.
Another object of the present invention is to provide a nonvolatile semiconductor memory device which makes it possible to further decrease the memory cell area and to simplify the steps of production.
A further object of the present invention is to provide a method of producing the above-mentioned nonvolatile semiconductor memory device and a method of writing/reading data using the above-mentioned device.
In order to accomplish the above-mentioned objects according to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells comprising a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in said semiconductor substrate, an electric charge-capturing film formed on a channel region between said pair of source and drain regions, and a gate electrode formed on said charge-capturing film and working as a control electrode, wherein said electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among said at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to said at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon said plurality of threshold voltages.
According to another aspect of the present invention, there is provided a method of producing nonvolatile semiconductor memory devices, comprising: a step of forming a multi-layer film by successively depositing a first insulating film, a first dielectric film working as an electric charge accumulation layer, a second insulating film, a second dielectric film working as an electric charge accumulation layer, a third insulating film, a third dielectric film working as an electric charge accumulation layer, and a fourth insulating film on a predetermined region on a semiconductor substrate; a step of forming an electrically conducting layer on said multi-layer film and forming a resist thereon in a shape that meets the shape of a gate electrode; a step of forming an electric charge-capturing film and a gate electrode in the shape of said resist by removing said multi-layer film and said electrically conducting layer by using said resist as a mask; and a step of forming a source region and a drain region by adding impurities having a type of electric conduction opposite to that of said semiconductor substrate to a surface region of said semiconductor substrate by using said resist as a mask.
According to a further aspect of the present invention, there is further provided a method of producing nonvolatile semiconductor memory devices, comprising: a step of forming a trench in a recessed shape at a predetermined position on a semiconductor substrate; a step of forming a multi-layer film by successively depositing a first insulating film, a first dielectric film working as an electric charge accumulation layer, a second insulating film, a second dielectric film working as an electric charge accumulation layer, a third insulating film, a third dielectric film working as an electric charge accumulation layer, and a fourth insulating film so as to cover the whole surface of said semiconductor substrate; a step of forming an electrically conducting layer so as to cover said multi-layer film; a step of forming an electric charge-capturing film of an L-shape and a gate electrode so as to span over a side wall of said trench and a portion of the bottom in contact with said side wall by subjecting the whole region where said electrically conducting layer is formed to anisotropic dry etching; and a step of forming a source region and a drain region by adding impurities having a type of electric conduction opposite to that of said semiconductor substrate to the surface region of said semiconductor substrate by masking only the region of said gate electrode.
In a preferred embodiment of the invention, said source region is formed relative to said gate electrode via said electric charge-capturing film on a region on the bottom of said trench other than the region where said gate electrode is formed, and said drain region is formed relative to said gate electrode via said electric charge-capturing film on a region on said semiconductor substrate other than the region where said trench is formed. Also, the step for forming said multi-layer film includes steps for forming oxide films as said first to fourth insulating films, and steps for forming nitride films as said first to third dielectric films. Also, at least said second to fourth oxide films are formed maintaining the same thickness, and said first to third nitride films are formed maintaining the same thickness. Furthermore, said first to third nitride films are formed maintaining a thickness larger than that of said second to fourth oxide films.
In another preferred embodiment of the invention, said.second to fourth oxide films are formed maintaining thicknesses that successively increase from the lower layer toward the upper layer. Also, said first to third nitride films are formed maintaining thicknesses that successively increase from the lower layer toward the upper layer.
In a still another preferred embodiment of the invention, the step for forming said multi-layer film includes steps for forming oxide films as said first to fourth insulating films, and steps for forming polysilicon films as said first to third dielectric films. Also, at least said second to fourth oxide films are formed maintaining the same thickness, and said first to third polysilicon films are formed maintaining the same thickness. Furthermore, said first to third polysilicon films are formed maintaining a thickness larger than that of said second to fourth oxide films. Alternatively, said second to fourth oxide films are formed maintaining thicknesses that successively increase from the lower layer toward the upper layer. Also, said first to third polysilicon films are formed maintaining thicknesses that successively increase from the lower layer toward the upper layer.
According to a further aspect of the present invention, there is provided a method of writing data into the memory cells in a nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells comprising a semiconductor substrate of one type of electric conduction, a source region and a drain region of the opposite type of electric conduction formed in said semiconductor substrate, an electric charge-capturing film formed on a channel region between said source region and said drain region, and a gate electrode formed on said charge-capturing film, wherein said electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, said method of writing data into said memory cells comprising: a step of setting a write voltage to be applied to the portions of said memory cells depending upon a value of write data; said step including a sub-step of applying, to said gate electrode, a predetermined voltage at which an electric charge is allowed to tunnel through an insulating film on the lower side of a dielectric film that captures the electric charge corresponding to a data value but at which no electric charge is allowed to tunnel through an insulating film on the upper side thereof, concerning part of said write data.
This writing method may further include a sub-step of applying a voltage to the portions of said memory cells so as to form a state where the electric charge is captured by none of said at least three dielectric films, concerning the data other than said write data.
According to a yet further aspect of the present invention, there is provided a method of reading data stored in the memory cells in a nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells comprising a semiconductor substrate of one type of electric conduction, a source region and a drain region of the opposite type of electric conduction formed in said semiconductor substrate, an electric charge-capturing film formed on a channel region between said source region and said drain region, and a gate electrode formed on said charge-capturing film, wherein said electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, said method of reading data stored in said memory cells comprising: a step of applying a first predetermined voltage to said gate electrode in order to judge to which one of the two voltage ranges the memory state of the memory cell belongs, said two voltage ranges being obtained by dividing into two a plurality of continuous ranges of threshold voltages that are set depending upon the values of the data that are read out; a step of judging whether a threshold voltage is higher than said first voltage or not upon detecting a current that flows between said source region and said drain region; a step of specifying a voltage range to which the memory state of said memory belongs based upon said judged result; a step of applying a second predetermined voltage to said gate electrode in order to judge to which one of the two voltage ranges the memory state of said memory cell belongs, said two voltage ranges being obtained by dividing said specified voltage into two; a step of judging whether a threshold voltage is higher than said second voltage or not upon detecting a current that flows between said source region and said drain region; and a step of specifying a voltage range to which the memory state of said memory belongs based upon said judged result; said steps being repeatively executed until a sole voltage range is specified to which the memory state of said memory cell belongs.